New computing system paradigms are being considered as power consumption in the face of ever increasing clock speeds becomes a larger concern. One of these new paradigms attempts to lower the power consumption of system memory which has traditionally been implemented with dynamic random access memory (DRAM) technology. DRAM technology is based on storing charge in capacitive cells that need continuous refreshment. The continuous refreshment, combined with higher clock speeds and denser cell packing densities has caused DRAM based system memories to become potentially too power hungry. DRAM technology still has superior (i.e., lower) access times as compared to other competing storage technologies, however.
A new paradigm, observed in FIG. 1, has emerged that uses two different types of memory technology within the system memory 103 of a computing system 100. Under this new paradigm system memory 103 is viewed as having two components: “near memory” 101 and “far memory” 102. Near memory 101 is composed of faster DRAM but acts as a caching layer for far memory 102. Far memory 102 may be implemented, for instance, with non volatile phase change memory (e.g., phase change memory and switch (PCMS)) that, although slower than DRAM, can be denser and consumes less power than DRAM. As such, system memory 103 as a whole has the potential to have more storage and consume less power because of the use of denser, less power hungry phase change technology for far memory 102. The penalty of using slower phase change technology is compensated for at least somewhat by using a (e.g., thin) layer of DRAM in near memory 101 as a caching layer for far memory 102. Here, if more frequently used information is kept in DRAM the access times of reaching such information will be improved.
The use of a near memory and far memory concept in system memory creates new opportunities for system wide speed-ups.